BIMSA
YMSC-BIMSA Quantum Information Seminar
Shallow neural network for real-time fault-tolerant decoding of surface codes
Shallow neural network for real-time fault-tolerant decoding of surface codes
Organizer
Speaker
Yicong Zheng
Time
Friday, November 26, 2021 9:30 AM - 12:15 PM
Venue
JCY-1
Online
Tencent 953 7541 0477
(2024)
Abstract
To experimentally implement fault-tolerant quantum computation (FTQC) on surface codes, high- performance fast decoding becomes essential for real-time fault-tolerant quantum error correction (FT-QEC) due to the short lifetime of qubits in the lab. A decoder based on neural network (NN) is promising since once trained, it is easy to parallelize on specific hardware, and execute in a short constant time. However, the use of NN decoder for fault-tolerant decoding in practical noise has not been studied thoroughly. Besides, the NN decoders are hard to train when the distance L is large due to the quick growth of the complexity of the networks. In this paper, we first propose a general framework to construct and train fault-tolerant NN decoder (FTNND). Then, we propose a systematical way to construct a fast and scalable NN decoder based on shallow depth convolutional neural network (CNN) inspired by the Renormalization Group (RG) decoder for arbitrary distance. The depth of such NN decoder grows slowly as O(log L), putting a small lower bound for the decoding latency. Our shallow CNN decoders outperform the standard maximum perfect matching algorithm in all error rate regions when syndrome measurement is perfect, and achieve an accuracy threshold around 1% for depolarization noise in the circuit level. Finally, we propose a general micro-architecture for FTNND to fully utilize the computation power of specific hardware like FPGA or ASIC. With such micro-architecture, for the first time, we deploy the FTNND for L = 5 on Intel Stratix 10 SX FPGA with decoding latency around 1μs, which paves the road for real-time FT-QEC in the near term experiments.