北京雁栖湖应用数学研究院 北京雁栖湖应用数学研究院

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关于我们
院长致辞
理事会
协作机构
参观来访
人员
管理层
科研人员
博士后
来访学者
行政团队
学术研究
研究团队
公开课
讨论班
招生招聘
教研人员
博士后
学生
会议
学术会议
工作坊
论坛
学院生活
住宿
交通
配套设施
周边旅游
新闻
新闻动态
通知公告
资料下载
清华大学 "求真书院"
清华大学丘成桐数学科学中心
清华三亚国际数学论坛
上海数学与交叉学科研究院
BIMSA > YMSC-BIMSA量子信息讨论班 Shallow neural network for real-time fault-tolerant decoding of surface codes
Shallow neural network for real-time fault-tolerant decoding of surface codes
组织者
刘正伟
演讲者
郑一聪
时间
2021年11月26日 09:30 至 12:15
地点
JCY-1
线上
Tencent 953 7541 0477 (2024)
摘要
To experimentally implement fault-tolerant quantum computation (FTQC) on surface codes, high- performance fast decoding becomes essential for real-time fault-tolerant quantum error correction (FT-QEC) due to the short lifetime of qubits in the lab. A decoder based on neural network (NN) is promising since once trained, it is easy to parallelize on specific hardware, and execute in a short constant time. However, the use of NN decoder for fault-tolerant decoding in practical noise has not been studied thoroughly. Besides, the NN decoders are hard to train when the distance L is large due to the quick growth of the complexity of the networks. In this paper, we first propose a general framework to construct and train fault-tolerant NN decoder (FTNND). Then, we propose a systematical way to construct a fast and scalable NN decoder based on shallow depth convolutional neural network (CNN) inspired by the Renormalization Group (RG) decoder for arbitrary distance. The depth of such NN decoder grows slowly as O(log L), putting a small lower bound for the decoding latency. Our shallow CNN decoders outperform the standard maximum perfect matching algorithm in all error rate regions when syndrome measurement is perfect, and achieve an accuracy threshold around 1% for depolarization noise in the circuit level. Finally, we propose a general micro-architecture for FTNND to fully utilize the computation power of specific hardware like FPGA or ASIC. With such micro-architecture, for the first time, we deploy the FTNND for L = 5 on Intel Stratix 10 SX FPGA with decoding latency around 1μs, which paves the road for real-time FT-QEC in the near term experiments.
北京雁栖湖应用数学研究院
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